The present invention relates to a stencil mask to be used for an electron beam exposure, an ion-beam exposure and an X-ray beam exposure and a method of forming the stencil mask.
The stencil mask has a pattern of opening to be used for an electron beam exposure, an ion-beam exposure and an X-ray beam exposure in order to form a pattern over a metal thin film or a semiconductor substrate. The stencil mask is thus used as a mask to carry out an exposure to the resist film applied over the metal thin film or the semiconductor substrate in order to form a first resist pattern. The opening pattern of the stencil mask allows transmission of the electron beam, the ion-beam exposure or the X-ray beam and irradiation thereof onto the resist film.
An available wafer for the stencil mask may comprise combined wafers of a first silicon substrate having a pattern and a second silicon substrate serving as a supporting substrate. Another wafer for the stencil mask may comprise a single silicon substrate having an impurity doped epitaxial silicon layer. Usually, the combined wafers are often used. In any event, the stencil mask may comprise combined wafers of a first silicon substrate having a pattern and a second silicon substrate serving as a supporting substrate. The second silicon substrate as the supporting substrate is to prevent any deformation of the stencil mask. The stencil mask is so placed in an exposure system that the second silicon substrate is positioned under the first silicon substrate which will have a pattern. The second silicon substrate supports the first silicon substrate and prevents any deformation of the first silicon substrate. An etching stopper layer is often interposed between the first and second silicon substrates for protecting the first silicon substrate from any over-etching when the second silicon substrate is etched. This interposed layer serving as the etching stopper layer may comprise an inorganic layer such as a silicon dioxide layer. In Japanese laid-open patent publication No. 5-216216, it is disclosed that a first conventional stencil mask comprises the combined first and second silicon substrate, between which the inorganic etching stopper layer is interposed. Further, this publication also discloses that a second conventional stencil mask comprises the combined first and second silicon substrate, between which an ion-implanted layer is interposed.
FIGS. 1A through 1E are fragmentary cross sectional elevation views illustrative of a first conventional method of forming a first conventional stencil mask.
With reference to FIG. 1A, an inorganic film 112 of silicon dioxide having a thickness of 1 micrometer is deposited on a first silicon substrate 111.
With reference to FIG. 1B, a second silicon substrate 113 is placed on the inorganic film 112. A heat treatment is carried out at a temperature of 1100xc2x0 C. for two hours, thereby to combine the first and second silicon substrates 111 and 113 to each other.
With reference to FIG. 1C, the second silicon substrate 113 is polished to reduce the thickness thereof to about 30 micrometers. First and second passivation inorganic films 114-1 and 114-2 of silicon dioxide having a thickness of 500 nanometers are formed on both surfaces of the combine the first and second silicon substrates 111 and 113 respectively. A first resist pattern is formed on the first passivation inorganic film 114-1 on the first silicon substrate 111 by use of a lithography technique. The first resist pattern is used as a mask for carrying out a selective etching to the first passivation inorganic film 114-1 on the first silicon substrate 111 for selectively removing the first passivation inorganic film 114-1, so that a center region of the bottom surface of the first silicon substrate 111 is shown. This first resist pattern is further used to carry out a back etching process as a wet etching to the first silicon substrate 111 by use of an ethylene amine pyrocatechol solution, so that a center region of the bottom surface of the inorganic film 112 is shown.
With reference to FIG. 1D, the first and second passivation inorganic films 114-1 and 114-2 are completely removed. A second resist pattern 115 is formed on a top surface of the second silicon substrate 113 by use of a lithography technique.
With reference to FIG. 1E, the second resist pattern 115 is used as a mask for carrying out a selective etching to the second silicon substrate 113 and the inorganic film 112 to form penetrating openings 200, whereby a stencil mask is completed which is superior in mechanical strength and high thermal stability.
In accordance with the first conventional stencil mask, the number of the fabrication processes is remarkably reduced. It is also easy to form the etching stopper interposed between the first and second silicon substrates. The first conventional stencil mask is capable of cutting an electron beam under an acceleration voltage of 50 kV. The first conventional stencil mask is also superior in thickness uniformity. The silicon dioxide film as the interposed etching stopper may be replaced with a silicon nitride film.
FIGS. 2A through 2E are fragmentary cross sectional elevation views illustrative of a second conventional method of forming a second conventional stencil mask.
With reference to FIG. 2A, an ion-implantation is carried out at an acceleration voltage in the range of 50-100 kV and a dose of 1E20/cm 2 for ion-implanting boron ions 142 into an upper region of a silicon substrate 111 to form an ion-implanted region 141 in the upper region of the silicon substrate 111.
With reference to FIG. 2B, a silicon epitaxial layer 143 is formed on the ion-implanted region 141 of the silicon substrate 111. First and second passivation silicon nitride films 144-1 and 144-2 on the bottom surface of the silicon substrate 111 and on the silicon epitaxial layer 143, respectively.
With reference to FIG. 2C, a first resist pattern not illustrated is formed on the first passivation silicon nitride film 144-1 by use of a lithography technique. The first resist pattern not illustrated is used as a mask for carrying out a selective etching to the first passivation silicon nitride film 144-1 on the bottom surface of the silicon substrate 111 for selectively removing the first passivation silicon nitride film 144-1, so that a center region of the bottom surface of the silicon substrate 111 is shown. This first resist pattern is further used to carry out a back etching process as a wet etching to the silicon substrate 111 by use of an ethylene amine pyrocatechol solution, so that a center region of the ion-implanted region 141 is shown. The first and second passivation silicon nitride films 144-1 and 144-2 are completely removed.
With reference to FIG. 2D, a second resist pattern 145 is formed on a top surface of the silicon epitaxial layer 143 by use of an electron beam lithography technique.
With reference to FIG. 2E, the second resist pattern 145 is used as a mask for carrying out a selective etching to the silicon epitaxial layer 143 and the ion-implanted region 141 to form penetrating openings 200, whereby a stencil mask is completed.
In accordance with the second conventional stencil mask, the ion-implanted region 141 serves as an etching stopper to the etching process to the silicon substrate 111 from the bottom side.
The first conventional stencil mask has a lamination structure of the silicon substrate, the silicon dioxide film and the silicon substrate. The second conventional stencil mask has a lamination structure of the silicon substrate, the ion-implanted region, and the impurity doped silicon epitaxial layer.
The above described first and second conventional fabrication processes have a problem in variation in etching rate of the back etching process for etching the silicon substrate serving as the supporting substrate. It is ideal for the back etching process that an etching rate is uniform in a plane vertical to an etching direction. The etching direction is vertical to the wafer surface. Namely, it is ideal for the back etching process that the etching rate is uniform in the plane vertical to the wafer surface. This means that an etching depth is kept uniform in the plane vertical to the wafer surface during the back etching process. If the back etching is stopped at an intermediate depth of the wafer, it is ideal that an etched surface has a high planarity with no over-etching nor under-etching.
Undesirably, during the etching process, the etching rate is not uniform in the plane vertical to the wafer surface and the etching depth varies in the plane vertical to the wafer surface. If the back etching is stopped at an intermediate depth of the wafer, it is undesirable that an etched surface has a surface roughness with over-etching and under-etching.
If during the etching process, the etching rate varies in the plane vertical to the wafer surface, then a stress due to the etching is non-uniformly applied in the wafer surface. If an abrupt stress is concentrated into a local part of the wafer, the stress applied part shows a strain such as a bend, a twist, a stretch or expansion. As a result, the pattern formation region of the stencil mask shows a deformation non-uniformly, whereby the pattern of the stencil mask has a distortion. In summary, the variation in etching rate in the plane vertical to the wafer surface causes a distortion of the wafer, and then the wafer is patterned to form a stencil mask pattern with a distortion, resulting in a deterioration in accuracy in the stencil mask pattern.
The reason why the etching rate varies in the plane vertical to the wafer surface is that the silicon substrate varies in the impurity concentration in the plane vertical to the wafer surface. If the impurity is boron and the etchant is an alkali solution such as a potassium hydroxide (KOH) solution, then an increase in the impurity concentration of the silicon substrate causes a decrease in etching rate. If the impurity is phosphorus and the etchant is fluorine acid solution, then an increase in the impurity concentration of the silicon substrate causes an increase in etching rate. It is, therefore, possible to solve the above problem by use of the silicon wafer having a uniform impurity-concentration in the plane vertical to the wafer surface.
The silicon wafer having a uniform impurity-concentration in the plane vertical to the wafer surface is, however, expensive. Once the stencil mask is completed, then the silicon substrate as the supporting substrate is free from any influence in characteristics thereof due to non-uniformity or variation in impurity concentration, for which reason it is undesirable in view of the cost to use an expensive wafer having a uniformity in impurity concentration in the plane vertical to the wafer surface.
The above first and second conventional techniques are further engaged with another problem in deteriorated etching accuracy, particularly this problem is serious to the above second conventional technique. The ion-implanted region of the silicon substrate causes the etching rate to be delayed but is imperfect as the etching stopper. Namely, the ion-implanted region of the silicon substrate may be etched. The silicon dioxide film interposed between the first and second silicon substrates is lower in etching rate than the ion-implanted region of the silicon substrate, but may also be etched. If the interposed layer is over-etched to the supporting silicon substrate, then the stencil mask pattern is defective. If the etched surface has a surface roughness due to over-etching and/or under-etching and a pattern-formed region of the stencil mask varies in thickness, then the stencil mask is deformed non-uniformly due to an applied stress which is caused by the fact that the stencil mask is heated by irradiation of electron beam. As a result, the stencil mask pattern has a distortion and is deteriorated in pattern accuracy.
In the above circumstances, it had been required to develop a novel stencil mask free from the above problem.
Accordingly, it is an object of the present invention to provide a novel stencil mask free from the above problems.
It is a further object of the present invention to provide a novel stencil mask allowing a uniform etching rate in the plane vertical to the wafer surface during the back etching process to the supporting silicon substrate.
It is a still further object of the present invention to provide a novel stencil mask having a highly accurate pattern.
It is yet a further object of the present invention to provide a novel method of forming a stencil mask free from the above problems.
It is further an object of the present invention to provide a novel method of forming a stencil mask allowing a uniform etching rate in the plane vertical to the wafer surface during the back etching process to the supporting silicon substrate.
It is moreover an object of the present invention to provide a novel method of forming a stencil mask having a highly accurate pattern.
In accordance with the present invention, the supporting layer is uniform in etching rate in a plane vertical to a surface of the supporting layer and generally decreases in etching rate in a direction toward a top surface of the supporting layer. For example, the supporting layer has a multi-layered structure including a top layer which is lowest in etching rate in all layers of the multi-layered structure forming the supporting layer. The supporting layer may comprise the top and bottom layers, wherein the bottom layer is higher in etching rate than the top layer. The back etching process for selectively etching the supporting layer decreases the etching rate as the back etching process is progressed. As the etching rate is decreased, the variation in etching rate in the plane vertical to the wafer surface is also suppressed. Even if the etching rate varies in the initial step for etching the supporting layer at a high etching rate, then as the back-etching process is progressed, the etching rate is decreased thereby to suppress the variation in etching rate in the plane vertical to the wafer surface, whereby the in-plane uniformity of the etching rate becomes high as the back etching is progressed, and thus a final back-etched surface has a high planarity. Therefore, a pattern-formed region of the finally formed stencil mask is highly uniform in thickness with no over-etching nor under-etching. As a result, the stencil mask has a highly accurate pattern.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.